The 4th Workshop on the Future of Computing Architectures (FOCA 2019) will be held on Friday October 18th, 2019 at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York. This event is a full-day workshop that provides a forum for invited students in a broad range of fields covering all aspects of architectures for the future of computing. Invited students are expected to showcase their work and interact with their peers and members of the IBM Research community.

The topics covered by FOCA 2019 include but are not limited to:

  • Architectures for artificial intelligence / machine learning.
  • Security- and reliability-aware architectures.
  • Architectures for cloud, high-performance computing, and data centers.
  • Next-generation memory architectures.
  • Parallel architectures.
  • Power‐efficient architectures and systems.
  • Embedded, IoT, reconfigurable, and heterogeneous architectures.
  • Architectures for emerging technology and applications.
  • Quantum computing, quantum circuit optimization.

Past Editions


Organizing Committee

  • Augusto Vega
  • Michael Healy
  • Karthik Swaminathan
  • Xinyu Que

Selection Committee

  • Alper Buyuktosunoglu
  • Bishwaranjan Bhattacharjee
  • Bruce D'Amora
  • Daniel Prener
  • Guerney Hunt
  • Guojing Cong
  • Hubertus Franke
  • Hyojin Sung
  • Jaime Moreno
  • Jinjun Xiong
  • Karthick Rajamani
  • Leopold Grinberg
  • Matthew Ziegler
  • Mihir Choudhury
  • Nandhini Chandramoorthy
  • Prabhakar Kudva
  • Pradip Bose
  • Ravi Nair
  • Sandhya Koteshwara
  • Xiaoxiong Gu
  • Zehra Sura


FOCA 2019 will be held in conjunction with the 2019 IBM IEEE CAS/EDS – AI Compute Symposium. Refer to the main venue to continue with the registration process.

Event Location

IBM T. J. Watson Research Center
1101 Kitchawan Rd
Yorktown Heights, NY 10598

Check main venue site for more information.


Friday October 18th, 2019
8:30 - 9:00am Breakfast
9:00 - 10:00am Keynote (Ruchir Puri, IBM Fellow and Chief Architect of IBM Watson)
10:00 - 10:30am "Alleviating Load Imbalance In Data Processing For Large-Scale Deep Learning"
Sarunya Pumma (Virginia Tech)
10:30 - 11:00am "MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation"
Lillian Pentecost (Harvard University)
11:00 - 11:15am Coffee Break
11:15 - 11:45am "Morpheus: Evading Attackers with Hardware-Based Ensembles of Moving Target Defenses"
Mark Gallagher (University of Michigan)
11:45am - 12:15pm "Rethinking Computer Architecture to Enable Low-Cost Security"
Gururaj Saileshwar (Georgia Tech)
12:15 - 1:00pm Lunch
1:00 - 2:00pm Quantum Lab Tour & Break
2:00 - 2:30pm "Hitting an Accelerator Wall: When Specialized Chips Meet the End of Moore's Law"
Adi Fuchs (Princeton University)
2:30 - 3:00pm "TBD"
Radha Venkatagiri (University of Illinois at Urbana-Champaign)
3:00 - 3:30pm Coffee Break
3:30 - 4:00pm "Keystone: A Framework for Architecting TEEs"
Dayeol Lee (University of California, Berkeley)
4:00 - 4:30pm "Post-Quantum Secure Digital Signatures on Embedded Systems"
Wen Wang (Yale University)
4:30 - 5:30pm Panel Session (details to be announced)
5:30pm Concluding Remarks


Augusto Vega is a Research Staff Member at IBM T. J. Watson Research Center involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He holds M.S. and Ph.D. degrees from Polytechnic University of Catalonia (UPC), Spain.

Michael Healy is a Research Staff Member at IBM T. J. Watson Research Center. His research interests cover a wide range of topics from low-level processor design to high-level system architecture. Michael's current work focuses on the memory subsystem. He also explores the use of 3D stacked memories such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC). He graduated from the Georgia Institute of Technology with B.S., M.S., and Ph.D. degrees in Computer Engineering.

Karthik Swaminathan is a Research Staff Member at IBM T. J. Watson Research Center. His research interests include power-aware architectures, domain-specific accelerators and emerging device technologies in processor design. He is also interested in architectures for approximate and cognitive computing, particularly in aspects related to their reliability and energy efficiency. He holds a Ph.D. degree from Penn State University.

Xinyu Que is a Research Staff Member in the Data Centric Systems Co-Design department at the T. J. Watson Research Center. He received his M.S. degree in Computer Science and Engineering from University of Connecticut and Ph.D. degrees in Computational Science and Software Engineering from Auburn University. Xinyu has broad interests in high performance computing and large-scale graph analytics.